Exemplary embodiments relate generally to a method of forming a semiconductor memory device and, more particularly, to a method of forming a semiconductor memory device, which forms patterns of different line widths at the same time.
Patterns forming a semiconductor device are formed using a photolithography process. The photolithography process includes a process of forming a photoresist layer on a target layer and a process of forming photoresist patterns by exposing and developing the photoresist layer. The exposed regions of the target layer are removed by using an etch process employing the photoresist patterns as an etch mask. The target layer is a material layer for the patterns of the semiconductor device or a hard mask layer formed on the material layer for the patterns of the semiconductor device.
If the target layer is the hard mask layer, a process of removing the exposed regions of the material layer for the patterns of the semiconductor device by using an etch process employing hard mask patterns, formed by etching the hard mask layer, as an etch mask is further performed.
When the patterns of the semiconductor device are formed by performing a series of the processes, an interval between the patterns and the width of each pattern are determined by an interval between the photoresist patterns and the width of each photoresist pattern. However, the exposure resolution limit may cause a limitation of the interval between the photoresist patterns and the width of each photoresist pattern. In order to overcome the exposure resolution limit, spacer patterning technology using spacers as an etch mask is being developed.
A process of forming the spacers includes a process of forming partition patterns on the target layer, a process of forming a spacer layer on a surface of the partition patterns, a process of etching a portion of the spacer layer to expose the partition patterns, and a process of removing the exposed partition patterns. In this case, since the width of each of the spacers formed by a series of the processes is determined by a deposition thickness of the spacer layer, the exposure resolution limit can be overcome and the photoresist patterns can be finely formed.
If the patterns of the semiconductor device are formed using the spacer patterning technology, the patterns can be formed finer than the exposure resolution limit because the width of each of the patterns is identical with the width of the spacer.
However, each of patterns formed in a specific region of the semiconductor device has a greater width than the spacer. For example, in case of the gate lines of a NAND flash memory device, the gate lines include word lines formed in a memory cell region and select lines formed in a select transistor region. In general, the word lines are formed to have finer line widths than the exposure resolution limit in order to improve the degree of high integration of semiconductor devices, and the select lines are formed to have wider widths than the word lines.
If the patterns of a semiconductor device are formed by using the spacers as an etch mask, however, the patterns of the semiconductor device have the same line width. Accordingly, there is a need for a method of forming patterns of different line widths (e.g., the word lines and the select lines) at the same time.